An interrupt handler contains the following instruction sequence at the end. The purpose of these instructions is to clear the interrupt request in the interrupt controller and then safely re-enable interrupts.
STR r0, [r1] ; write to interrupt controller register to clear interrupt request
CPSIE i ; re-enable IRQ interrupts
Which of the following instructions should be placed at position
In a Cortex-A9 MPCore cluster with four processors, which of the processors can be interrupted by a software-generated interrupt?
Within the ARMv7 architecture, which one of the following features is unique to the ARMv7-A profile?
The following C function is compiled with hard floating point linkage.
float function(int a, float b, int c, float d);
Which register is used to pass argument c?
Literal pool loads to access constants at run-time can be minimized by:
Clicking the Start button in a debugger:
According to the AAPCS, how many bytes are used to store a C variable of type 'int' in memory?
In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:
CPU 0 and 1 are sleeping in low-power state following a WFI instruction. . CPU 2 is executing program code.
CPU 3 is sleeping in low-power state following a WFE instruction.
CPU 2 executes a SEV instruction. What is the effect on the system?
Which of the following features was added in version 2 of the ARM Architecture Advanced SIMD extensions?
The Cortex-A9 processor implements a feature called "small loop mode" which reduces power consumption when executing small loops by turning off instruction cache accesses. Which of the following statements describes a condition that must be satisfied for this mode to be enabled?
