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If the memory location 0x5000 contains 0Xffff0001, what is the value of r0 after the following instructions are executed?

MOV r1, #0x5000

LDRSH r0, [r1]

ADD r0, r0, #1

(Assume a little-endian memory system)

A.

0x00000002

B.

0xFFFF0002

C.

0xFFFF0001

D.

0xFFFFFFFE

When using an Operating System, which of the following operations can NOT typically be done by user processes?

A.

Reading the link register (R14)

B.

Reading data from the user stack

C.

Changing from ARM state to Thumb state

D.

Changing the interrupt mask bits (A, I, F) in the CPSR

A Programmer's View CPU model usually provides:

A.

Cycle-accurate simulation of the CPU.

B.

Instruction-accurate simulation of the CPU.

C.

Simulation of user-defined memory-mapped peripherals.

D.

Cycle-accurate simulation of the cache and memory system.

In an operating system environment, most applications are executed in which processor mode?

A.

Supervisor

B.

IRQ

C.

System

D.

User

A message passing system between two CPUs is implemented using data stored in a shared area of memory. To pass a message, the first CPU executes the instructions:

The second CPU receives the message using the instructions:

On both CPUs, r1 = 0x5000 and r2 = 0x6000. At which of the points A, B, C and D must Data Memory Barrier (DMB) instructions be placed in order to ensure messages are passed reliably and efficiently?

A.

A only

B.

C only

C.

B and C

D.

A and D

What is an "Entry point" in an application?

A.

A place where execution can start

B.

The location of the main () function

C.

The lowest address contained in a program image

D.

A location where the linker can store additional information

On an ARM processor that does not implement Security Extensions, which one of the following can be the starting address of the exception vector table?

A.

0xFFFFFFFF

B.

0xFFFFFFF0

C.

0xFFFF0000

D.

0x0000FFFF

What side-effect could using a debugger to read memory contents have?

A.

The memory contents could be set to zero

B.

Some memory contents could be rewritten

C.

The processor MMU pagetables could be modified

D.

The processor cache could be cleaned or/and invalidated

A standard performance benchmark is being run on a single core ARM v7-A processor. The performance results reported are significantly lower than expected. Which of the following options is a possible explanation?

A.

L1 Caches and branch prediction are disabled

B.

The Embedded Trace Macrocell (ETM) is disabled

C.

The Memory Management Unit (MMU) is enabled

D.

The Snoop Control Unit (SCU) is disabled

In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)

A.

VA == PA; No address translations; instructions and data are not cached

B.

VA! = PA; No address translations; instructions may be cached but not data

C.

VA == PA; Address translations take place; data may be cached but not instructions

D.

VA == PA; No address translations; instructions may be cached but not data