Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.
How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?
In which TWO of the following locations would a compiler typically place local variables? (Choose two)
What will be the contents of R2 after the execution of the following piece of code?
LDRR1, =0xAABBCCDD
MOV R2, #0x4
ANDSR1, R1, #0x4
ADDNE R2, R2, #0x4
An Advanced SIMD intrinsic has the prototype:
int16x4_t vmul_n_s16(int16x4_t a, int16_t b);
How many multiplications does this intrinsic compute?
The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?
When using the ARM Compiler (armcc), which of the following possible keywords can be used to remove padding bytes from a structure?
To ensure optimum efficiency when programming in C, what is the recommended maximum number of arguments to be passed to a function?
A development board is supplied with a Board Support Package (BSP) for a particular operating system. Which TWO of these items would you expect to find in the BSP? (Choose two)
Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?
Which of the following processor resources do NOT have to be saved or modified by the Linux scheduler during context switch?
